TP RAM的低功耗设计及应用
Low Power Design of TP RAM and Its Application
DOI: 10.12677/OJCS.2017.61001, PDF, HTML, XML, 下载: 1,734  浏览: 3,940  国家自然科学基金支持
作者: 周清军, 邢 静：西安培华学院中兴电信学院，陕西 西安
关键词: TP RAM；SP RAM；功耗优化；接口转换逻辑；TP RAM； SP RAM； Optimization of Power Consumption； Interface Logics of Conversion
摘要: 针对SoC中TP RAM的面积及功耗较大问题，提出一种优化设计方法。通过将SoC中的TP RAM替换成SP RAM，并在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。将文中方法应用于一款多核SoC芯片，该芯片经TSMC 28 nm HPM工艺成功流片，die size为10.7 mm × 11.9 mm，功耗为19.8 W。测试结果表明：优化后的RAM面积减少了24.5%，功耗降低了45.16%。
Abstract: As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is proposed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPM process. The chip occupies 10.7 mm × 11.9 mm of die area and consumes 19.8 W. The testing results indicate that the area of optimized RAM is reduced by 24.5%, and the power saving is 45.16%.
文章引用：周清军, 邢静. TP RAM的低功耗设计及应用[J]. 电路与系统, 2017, 6(1): 1-7. https://doi.org/10.12677/OJCS.2017.61001

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