一种基于FPGA的新型全数字锁相环的建模与分析

Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

摘要: 提出了一种新型的全数字锁相环，其采用自采样比例积分控制，使得锁相输出无静差，输出抖动小，并能根据数字鉴相器输入信号间相位误差的大小，调节数字环路滤波器的计数模数，在保证锁相环稳定性的同时，提高了锁相环锁定速度。本文基于该全数字锁相环各模块工作特性的分析，建立了全数字锁相环的数学模型，利用所得到的锁相环系统传递函数进行了性能参数分析，并给出了锁相环参数设计指导原则。论文最后通过实验测试验证了理论参数分析的正确性。

Abstract: This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter according to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper establishes the mathematical model of the ADPLL based on the analysis of the operating characteristic of each module. Using the obtained system transfer function, the paper analyzes the performance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper.