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Ramakrishnan, V. and Balsara, P.T. (2006) A wide-range, high-resolution, compact, CMOS time to digital converter. VLSI Design, 3-7 January 2006, 1063-9667.

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  • 标题: 基于延迟线内插法的时间间隔测量电路A Time Interval Measurement Circuit Based on Delay Line Interpolation

    作者: 张炜, 吴秋莉, 黄钰, 张春, 邓雨荣

    关键字: 延迟线内插法, 时间间隔测量, 延时链Delay Line Interpolation, Time Interval Measurement, Delay Cell

    期刊名称: 《Open Journal of Circuits and Systems》, Vol.4 No.1, 2015-02-13

    摘要: 在时间同步系统中,时间间隔的测量至关重要。提高时间间隔测量的精度,可以让整个定位系统的定位更精确。延迟线内插法是近年来广泛研究和采用的一种时间间隔测量方法。同时内插法结合电子计数器可以扩大测量量程,从而同时达到高精度、大量程的测量需求。本文针对定位系统时间间隔测量的需求,采用全定制芯片实现方式,在0.18 um COMS工艺下,实现了128级延时单元的延时链,仿真单级延时67 ps,实际测试该芯片的测量精度在1 ns以内。 Time interval measurement plays an important role in time synchronization system. Precise time interval measurement can improve the accuracy of positioning system. The delay line interpolation method with electron counter is widely used in recent years, which can meet the need of high accuracy as well as large ranging scale. This paper presents a full custom time interval measure-ment chip based on delay line interpolation circuits in 0.18 um COMS technology to satisfy the time interval measurement needs in positioning system and realizes 128-stage delay units. The simulation accuracy of single delay cell is 67 ps and the actual maximum measurement error is approximately 1 ns.

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