基于状态机与LFSR的FPGA“打地鼠”游戏系统设计

Design of FPGA “Whack-a-Mole” Game System Based on State Machine and LFSR

摘要: 随着可编程逻辑器件在互动娱乐领域的应用日益深入，本文设计并实现了一款基于FPGA的趣味“打地鼠”游戏机系统。该系统以Altera Cyclone IV系列芯片为控制核心，采用Verilog HDL进行全硬件逻辑描述，旨在提供一种高实时性、高可靠性的游戏解决方案。系统的核心亮点在于其精巧的逻辑架构：首先，利用多项式反馈逻辑构造线性反馈移位寄存器(LFSR)，高效地生成了控制LED地鼠位置的伪随机序列；其次，设计了一套包含空闲、激活和防连击等待三个主状态的有限状态机，它不仅实现了击中计分、超时扣血等基础游戏规则，还通过引入按键上升沿检测机制，成功解决了长按作弊与连击误判的技术难题。此外，系统内置了基于分数梯度的动态难度自适应算法，能够根据玩家表现自动调整地鼠的出现频率与停留时间，极大地增强了游戏的可玩性与挑战性。最终，在小梅哥AC101开发板上的综合板级验证表明：系统逻辑正确，状态流转无误；按键消抖稳定，随机机制有效；动态难度调节与音视频反馈现象均与设计预期完全一致。该设计方案为基于FPGA的反应测试类游戏平台开发提供了一种可靠且可扩展的实现范例。

Abstract: With the deepening application of programmable logic devices in the field of interactive entertainment, this paper designs and implements a fun “Whack-a-Mole” game console system based on FPGA. The system takes the Altera Cyclone IV series chip as the control core and uses Verilog HDL for full hardware logic description, aiming to provide a high-real-time and high-reliability game solution. The core highlight of the system lies in its ingenious logic architecture: Firstly, a Linear Feedback Shift Register (LFSR) is constructed using polynomial feedback logic, which efficiently generates a pseudo-random sequence to control the positions of the LED “moles”. Secondly, a Finite State Machine comprising three main states—Idle, Active, and Anti-double-click Wait—is designed. It not only realizes basic game rules such as hit scoring and timeout health deduction, but also successfully solves the technical challenges of long-press cheating and double-click misjudgment by introducing a button rising-edge detection mechanism. Furthermore, the system incorporates a dynamic difficulty self-adaptation algorithm based on score gradients, which automatically adjusts the appearance frequency and residence time of the moles according to the player’s performance, greatly enhancing the playability and challenge of the game. Finally, comprehensive board-level verification on the AC101 development board shows that: the system logic is correct, and the state transitions are error-free; the button debouncing is stable, and the random mechanism is effective; the dynamic difficulty adjustment and audio-visual feedback phenomena are completely consistent with the design expectations. This design scheme provides a reliable and scalable implementation paradigm for the development of reaction-testing game platforms based on FPGA.