|
[1]
|
Sharangpani, H. and Barton, M.L. (1994) Statistical Analysis of Floating Point Flaw in the Pentium Processor. Intel Corporation.
|
|
[2]
|
Bryant, R.E. (1986) Graph-based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, 35, 677-691. [Google Scholar] [CrossRef]
|
|
[3]
|
Bryant, R.E. and Chen, Y. (2001) Verification of Arithmetic Circuits Using Binary Moment Diagrams. International Journal on Software Tools for Technology Transfer, 3, 137-155. [Google Scholar] [CrossRef]
|
|
[4]
|
Chen, Y. and Bryant, R.E. (1995) Verification of Arithmetic Circuits with Binary Moment Diagrams. 32nd Design Automation Conference, San Francisco, 12-16 June 1995, 535-541. [Google Scholar] [CrossRef]
|
|
[5]
|
Biere, A. (2016) Collection of Combinational Arithmetic Miters Submitted to the SAT Competition 2016. SAT Competition 2016, 65-66.
|
|
[6]
|
Biere, A. (2016) Weaknesses of CDCL Solvers, August 2016. Fields Institute Workshop on Theoretical Foundations of SAT Solving. http://www.fields.utoronto.ca/talks/weaknesses-cdcl-solvers
|
|
[7]
|
Kaufmann, M. and Moore, J.S. (2019) ACL2 Version 8.2. http://www.cs.utexas.edu/users/moore/acl2/
|
|
[8]
|
Kaufmann, D. (2020) AMulet 1.5. https://github.com/d-kfmnn/amulet
|
|
[9]
|
Buchberger, B. (1965) Ein Algorithmuszum Auffinden der Basiselemente des Restklassenringesnacheinemnulldimensiona-lenPolynomideal. Ph.D. Thesis, University of Innsbruck.
|
|
[10]
|
Ciesielski, M.J., Su, T., Yasin, A. and Yu, C. (2019) Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 1346-1357.
|
|
[11]
|
Kaufmann, D. (2020) Formal Verification of Multiplier Circuits using Computer Algebra. Ph.D. Thesis, Johannes Kepler University Linz.
|
|
[12]
|
Mahzoon, A., Große, D. and Drechsler, R. (2019) RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. Proceedings of the 56th Annual Design Automation Conference 2019, Las Vegas, 2-6 June 2019, 1-6. [Google Scholar] [CrossRef]
|
|
[13]
|
Kaufmann, D., Biere, A. and Kauers, M. (2019) Verifying Large Multipliers by Combining SAT and Computer Algebra. 2019 Formal Methods in Computer Aided Design (FMCAD), San Jose, 22-25 October 2019, 28-36 [Google Scholar] [CrossRef]
|
|
[14]
|
Cox, D., Little, J. and O’Shea, D. (2015) Ideals, Varieties, and Algorithms. 4th Edition, Springer-Verlag.
|
|
[15]
|
Becker, T., Weispfenning, V. and Kredel, H. (1993) Gröbner Bases, volume141 of Graduate Texts in Mathematics. Springer. [Google Scholar] [CrossRef]
|
|
[16]
|
Sayed-Ahmed, A., Groβe, D., Kühne, U., Soeken, M. and Drechsler, R. (2016) Formal Verification of integer Multipliersby Combining Gröbner basis with Logic Reduction. DATE 2016: 2016 Design, Automation & Test in Europe Conference & Exhibition, Dresden, 14-18 March 2016, 1048-1053. [Google Scholar] [CrossRef]
|
|
[17]
|
Biere, A. (2017) The AIGER And-Inverter Graph (AIG) Format, 20071012. Institute for Formal Models and Verification.
|
|
[18]
|
Kernighan, B.W. and Ritchie, D.M. (1988) The C Programming Language. 2nd Edition, Prentice Hall.
|
|
[19]
|
Niemetz, A., Preiner, M. and Biere, A. (2015) Boolector 2.0 System Description. Journal on Satisfiability, Boolean Modeling and Computation, 9, 53-58 [Google Scholar] [CrossRef]
|