供应三维芯片的电源与频率信号稳定调整机制之设计

A Supply Voltage and Clock Signal Stabilized Mechanism Design and Implementation for 3D Chip

摘要: 本论文设计是结合3D IC的电源质量量测、电源管理机制技术与频率供给管理机制并进行芯片验证。为了精确的评估所产生的电源问题，我们需设计了一个内嵌式的电压量测设计(Built-In Voltage Measurement- BIVM)来量测电压准位，了解电压降的情形，将电压降的情形侦测后再以数字方式来控制电源开关，以便调节电压准位，以稳定电压供应，来做电源质量管理。我们利用控制PMOS的Power Switch Module (PSM)的开启程度来调节电压，更利用电源压降量测电路进行回授控制电源管理机制，同时调节电源供应与频率供给，如此不只可以让使用者了解当时的电源压降外，还可以让电路自行调节到稳定的状态，并达到减少多核心或3D IC功率消耗的目的。

Abstract: This design includes the voltage measurement, management and frequency stabilization mechanisms for 3D IC. The circuit voltage levels are sensed by the Built in Voltage Measurement circuit (Built-In Voltage Measurement- BIVM). From the voltage level measurement result, the feedback control circuit can decide the turned on PSM quantities. However, the frequency supply to the circuit needs to degrade in this situation to prevent the supplied voltage level from degrading continually. The feedback mechanism is to turn on less/more PSM and maintain the voltage level stabilization. This mechanism allows the multicore design stable operation, with regardless to the new circuit loading added to the system dynamically. The digitalized voltage and frequency stabilization mechanism are applied for the multicore or the 3D staking design.