金属纳米晶存储器存储特性的模拟
Simulation of Memory Characteristics ofMetal Nanocrystals
摘要: 采用一个简单的电学瞬态模型,在理论上模拟Pt、Au、Ni、Al金属纳米晶器件的数据保持、读入和擦除过程。在这个模型中,考虑量子限制效应、库仑阻塞效应、Si衬底表面势以及热激发效应的影响。随着纳米晶直径的增大,隧穿氧化层厚度的增大,保持时间会增大。反之随着栅极电压的增大,隧穿氧化层厚度的减小,读入时间和擦除时间都会减小。在擦除过程中,当外加的反向偏压的绝对值减少到一定值的时候,擦除时间会急剧增大,这是因为需要通过热激发参与才能完成隧穿。对于不同的金属材料,由于它们的功函数不同,保持能力、读入速度和擦除速度相差较大。Pt纳米晶存储器的数据保持能力最强,而Al纳米晶存储器的读入速度和擦除速度较快。
Abstract: Using a transient electrical model, the charging, discharging and retentive processes in a metal nanocrystal (NC) memory were simulated. In this model, the impact of Si surface potential, Coulomb blockade effect, quantum confinement effect and thermal activation were taken into account. The NC memory with larger size can be programmed faster and has the longer retention time. The retention time increases with the increase of nanocrystal size or tunneling dielectric thickness. The program time and erase time decrease with the increase of the gate voltage or the decrease of tunneling dielectric thickness. For different metal materials, the retention time, program speed and erase speed of metal NC memory are not the same. For Pt, Au, Ni and Al, the retention time of Pt NC is the largest, and the program speed and erase speed of Al NC is the fastest.
文章引用:王蓓, 程佩红, 黄仕华. 金属纳米晶存储器存储特性的模拟[J]. 纳米技术, 2011, 1(3): 49-55. http://dx.doi.org/10.12677/nat.2011.13010

参考文献

[1] H. I. Hanafi, S. Tiwari and I. Khan. Fast and long retention-time nanocrystal memory. IEEE Transactions on Electron Devices, 1996, 43(9): 1553-1558.
[2] P. Dimitrakis, E. Kapetanakis, et al. MOS memory structures by very low energy implanted Si in thin SiO2. Materials Science and Engineering: B, 2003, 101(1-3): 14-18.
[3] Y. Shi, K. Saito, et al. Effects of traps on charge storage cha- racteristics in metal oxide semiconductor memory structures based on silicon nanocrystals. Journal of Applied Physics, 1998, 84(4): 2358-2360.
[4] Z. T. Liu, C. G. Lee, et al. Metal nanocrystal memories-Part I: device design and fabrication. IEEE Transaction on Electron Devices, 2002, 49(9): 1606-1631.
[5] C. H. Lee, J. Meteer, et al. Self-assembly of metal nanocrystal on ultrathin oxide for nonvolatile memory applications. Journal of Electronic Materials, 2005, 34(1): 1-11.
[6] J. J. Lee, Y. Harada, J. W. Pyun and D.-L. Kwong. Nickel na- nocrystal formation on HfO2 dielectric for nonvolatile memory device applications. Applied Physics Letters, 2005, 86(10): Arti- cle ID 103505-3.
[7] Z. Tan, S. K. Samanta, W. J. Yoo and S. Lee. Self-assembly of Ni nanocrystals on HfO2 and N-assisted Ni confinement for nonvolatile memory application. Applied Physics Letters, 2005, 86(1): Article ID 013107-3.
[8] M. She, T.-J. King. Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance. IEEE Tran- sactions on Electron Devices, 2003, 50(9): 1934-1940.
[9] W. Guan, S. Long, M. Liu, Q. Liu, Y. Hu, Z. Li and R. Jia. Mo- deling of retention characteristics for metal and semiconductor nanocrystal memories. Solid-State Electronics, 2007, 51: 806- 811.
[10] V. Beyer, J. von Borany and M. Klimenkov. A transient electrical model of charging for Ge nanocrystal containing gate oxides. Journal of Applied Physics, 2007, 101(9): Article ID 094507-7.
[11] V. Beyer, J. von Borany, M. Klimenkov and T. Müller. Cu- rrent-voltage characteristics of metal oxide semiconductor de- vices containing Ge or Si nanocrystals in thin gate oxides. Jour- nal of Applied Physics, 2009, 106(6): Article ID 064505.
[12] K. F. Schuegraf, C. Hu. Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation. IEEE Transactions on Electron Devices, 1994, 41(5): 761-767.
[13] Z. A. Weinberg. On tunneling in metal oxide silicon structures. Journal of Applied Physics, 1982, 53(7): 5052-5056.
[14] W.-C. Lee, C. Hu. Modeling CMOS tunneling Currents through ultrathin gate oxide due to conduction and valence band electron and hole tunnel. IEEE Transactions on Electron Devices, 2001, 48(7): 1366-1373.