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An Interleaved Parallel Boost Converter Voltage Spike Suppression Method Based on the SiC MOSFET
DOI: 10.12677/AEPE.2023.116021, PDF, HTML, XML, 下载: 177  浏览: 302

Abstract: The trend for high-power converters is high frequency, high efficiency, and high power density. Compared to traditional silicon-based power devices, the original MOSFET is widely used because of its fast switching speed, low switching losses, and high operating temperatures. However, in this way, MOSFETs are prone to voltage spikes and oscillations during high-speed shutdown, seriously threatening the reliable operation of the power converter. In response to this issue, this article provides a detailed analysis of the SiC MOSFET shutdown process and proposes corresponding suppression methods for the two factors that affect the shutdown voltage spike. To verify the effectiveness of the proposed method, an experimental platform was established. The experimental results show that the proposed method can effectively suppress voltage spikes generated during the shutdown process without significantly increasing switch losses.

1. 引言

Figure 1. Topology diagram of interleaved parallel Boost converter

2. 关断电压尖峰的机理分析

Figure 2. Topology diagram of Boost topology

Figure 3. Shutdown process diagram of SiC MOSFET

2.1. 关断延时阶段(t0~t1)

${V}_{gl}={R}_{g}{i}_{g}+{V}_{gs}+{L}_{g}\frac{\text{d}{i}_{g}}{\text{d}t}+{L}_{s}\frac{\text{d}{i}_{d}}{\text{d}t}$ (1)

${i}_{g}={C}_{iss}\frac{\text{d}{V}_{gs}}{\text{d}t}$ (2)

2.2. 关断延时阶段(t1~t2)

$\frac{\text{d}{V}_{ds}}{\text{d}t}=\frac{{i}_{g}}{{C}_{gd}}$ (3)

2.3. 电流下降阶段(t2~t3)

$\frac{\text{d}{i}_{d}}{\text{d}t}={g}_{m}\frac{\text{d}{V}_{gs}}{\text{d}t}$ (4)

$\frac{\text{d}{i}_{d}}{\text{d}t}=\frac{{V}_{gl}-{V}_{gs}}{{R}_{g}{g}_{m}/{C}_{iss}+{L}_{g}}$ (5)

${V}_{os}={V}_{ds}-{V}_{dc}=-{L}_{p}\frac{\text{d}{i}_{d}}{\text{d}t}$ (6)

${L}_{p}={L}_{s}+{L}_{d}$ (7)

2.4. 电流下降阶段(t3~t4)

${V}_{ds}={V}_{out}+{V}_{os}{\text{e}}^{-\alpha \left(t-{t}_{4}\right)}\mathrm{cos}\left[\omega \left(t-{t}_{4}\right)\right]$ (8)

${i}_{d}\left(t\right)={C}_{oss}\frac{\text{d}{v}_{ds}}{\text{d}t}$ (9)

$\alpha =\frac{{R}_{stray}}{2{L}_{p}}$ (10)

$\omega =\sqrt{\frac{1}{{C}_{oss}{L}_{p}}-{\alpha }^{2}}$ (11)

${C}_{oss}={C}_{gd}+{C}_{ds}$ (12)

3. 电压尖峰抑制方法

3.1. 减小SiC MOSFET关断时的电流

Figure 4. Boost converter with added RC absorption circuit

3.2. 降低SiC MOSFET的关断速度

$\frac{\text{d}V}{\text{d}t}=\frac{{V}_{g}-{V}_{miller}}{{C}_{gd}\ast {R}_{g}}$ (13)

Figure 5. Boost converter with c connected in parallel between DG

4. 试验验证及分析

4.1. RC吸收电路的效果验证

Table 1. Test parameters

Figure 6. Waveform without RC absorption at both ends of DS

Figure 7. Waveform with RC absorption at both ends of DS

4.2. 增大Cgd的效果验证

Figure 8. The detailed waveform of the turn-off of the non parallel capacitor between the DG of SiC MOSFET

Figure 9. The detailed waveform of the turn-off of the parallel capacitor between the DG of SiC MOSFET

5. 结论

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