DRAM 2T0C技术综述
Review of DRAM 2T0C Technology
摘要: DRAM作为计算机存储系统的核心组件，在HPC、云计算、AI等领域至关重要。然而，传统1T1C DRAM受电容缩放瓶颈、刷新功耗及制造复杂度等问题限制，难以满足先进制程需求。2T0C DRAM采用双晶体管架构，利用浮体效应、栅极耦合等机制存储电荷，实现高密度、低功耗及工艺兼容性提升。本研究分析2T0C DRAM的技术原理、结构设计及其相较于1T1C DRAM的优势，探讨数据保持、读写干扰、工艺变异等挑战，并综述器件优化、电路创新及先进制造工艺的应对策略。此外，结合CIM、3D集成等趋势，探讨其在HPC、嵌入式及新型存储中的应用价值。当前，三星、美光等厂商已展开2T0C DRAM研发，预计未来逐步进入量产。随着半导体工艺演进，2T0C DRAM有望成为下一代高密度、低功耗存储技术。然而，量子效应、工艺适配及产业链完善仍是关键挑战。未来研究将聚焦器件微缩、存算一体及异质集成，推动2T0C DRAM发展与产业化进程。
Abstract: As a core component of computer memory systems, DRAM plays a critical role in HPC, cloud computing, and AI. However, traditional 1T1C DRAM faces challenges such as capacitor scaling limitations, high refresh power consumption, and increasing fabrication complexity, restricting its scalability in advanced process nodes. To address these issues, 2T0C DRAM adopts a two-transistor architecture, utilizing floating-body effects and gate coupling mechanisms to store charge, thereby enhancing storage density, reducing power consumption, and improving process compatibility. This study analyzes the technical principles and structural design of 2T0C DRAM, highlighting its advantages over 1T1C DRAM while addressing challenges such as data retention, read/write disturbances, and process variations. Various optimization strategies, including device engineering, circuit design innovations, and advanced fabrication techniques, are also reviewed. Furthermore, considering emerging trends like CIM and 3D integration, we explore the potential applications of 2T0C DRAM in HPC, embedded systems, and next-generation memory technologies. Currently, leading memory manufacturers such as Samsung and Micron have initiated research on 2T0C DRAM, with commercialization expected in the near future. With the continuous advancement of semiconductor technology, 2T0C DRAM is poised to become a key candidate for next-generation high-density, low-power memory solutions. However, challenges such as quantum effects, process adaptation, and supply chain maturity remain critical. Future research will focus on device scaling, in-memory computing, and heterogeneous integration to accelerate the development and industrialization of 2T0C DRAM.
文章引用：孟家宇, 王晓芳. DRAM 2T0C技术综述[J]. 物理化学进展, 2025, 14(2): 127-136. https://doi.org/10.12677/japc.2025.142012

参考文献

[1] Zhu, Z., Kang, B., Zhang, J., Duan, X., Xiang, J., Yang, G., et al. (2023) Cell Structure and Process Integration of a Novel 2T0C Technology for High-Density Dram Application. 2023 China Semiconductor Technology International Conference (CSTIC), Shanghai, 26-27 June 2023, 1-4. [Google Scholar] [CrossRef] 
[2] Hwan Kong, S. and Shim, W. (2024) Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure. IEEE Transactions on Electron Devices, 71, 6633-6638. [Google Scholar] [CrossRef] 
[3] Yook, C. and Shim, W. (2024) Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part II: Adaptive Layer-Wise Refresh Technique. IEEE Transactions on Electron Devices, 71, 6639-6646. [Google Scholar] [CrossRef] 
[4] Kim, J., Kim, H., Kim, K., Shim, T., Hong, J. and Park, J. (2023) 3-Terminal IGZO FET Based 2T0C DRAM Combined Bit-Line Structure. ECS Meeting Abstracts, 2023, Article 1561. [Google Scholar] [CrossRef] 
[5] He, S., Li, H., Xu, G., Tang, X., Li, Y., Kim, J., et al. (2023) Modeling the Thermal Characteristics of Stacked 2T0C Memory Array Based on InGaZnO4 Thin-Film Transistors. IEEE Transactions on Electron Devices, 70, 6369-6374. [Google Scholar] [CrossRef] 
[6] Gu, C., Hu, Q., Zhu, S., Li, Q., Zeng, M., Kang, J., et al. (2024) First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel. IEEE Electron Device Letters, 45, 1764-1767. [Google Scholar] [CrossRef] 
[7] Ryu, S., Kang, M., Cho, K. and Kim, S. (2024) Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium-Tin-Gallium-Zinc Oxide Thin‐Film Transistors for the Multiply-Accumulate Operation. Advanced Materials Technologies, 9, Article ID: 2302209. [Google Scholar] [CrossRef] 
[8] Lu, W., Zhu, Z., Chen, K., Liu, M., Kang, B., Duan, X., et al. (2022) First Demonstration of Dual-Gate IGZO 2T0C DRAM with Novel Read Operation, One Bit Line in Single Cell, ION=1500 μA/μm@VDS=1V and Retention Time>300s. 2022 International Electron Devices Meeting (IEDM), San Francisco, 3-7 December 2022, 26.4.1-26.4.4. [Google Scholar] [CrossRef] 
[9] Lee, F., Tseng, P., Lin, Y., Lin, Y., Weng, W., Lin, N., et al. (2024) Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, 16-20 June 2024, 1-2. [Google Scholar] [CrossRef] 
[10] Chen, C., Xiang, J., Duan, X., Lu, C., Niu, J., Zhang, K., et al. (2023) First Demonstration of Stacked 2T0C-DRAM Bit-Cell Constructed by Two-Layers of Vertical Channel-All-Around IGZO FETs Realizing 4F2 Area Cost. 2023 International Electron Devices Meeting (IEDM), San Francisco, 9-13 December 2023, 1-4. [Google Scholar] [CrossRef] 
[11] Su, Y., Shi, M., Tang, J., Li, Y., Du, Y., An, R., et al. (2024) Monolithic 3-D Integration of Counteractive Coupling IGZO/CNT Hybrid 2T0C DRAM and Analog RRAM-Based Computing-in-Memory. IEEE Transactions on Electron Devices, 71, 3336-3342. [Google Scholar] [CrossRef] 
[12] Zheng, L., Wang, Z., Lin, Z. and Si, M. (2023) The Impact of Parasitic Capacitance on the Memory Characteristics of 2T0C DRAM and New Writing Strategy. IEEE Electron Device Letters, 44, 1284-1287. [Google Scholar] [CrossRef] 
[13] Zhu, X., He, Y., Wang, Z., Guo, H. and Zhu, H. (2024) 3D-Stacked 2T0C-DRAM Cells Using Al2O3/TiO2-Based 2DEG FETs. IEEE Electron Device Letters, 45, 1173-1176. [Google Scholar] [CrossRef] 
[14] Liang, J., Yuan, P., Yu, Y., Xiang, J., Zhu, Z., Zhou, M., et al. (2024) A Design Methodology for Highly Reliable Operation for 2T0C Dynamic Random Access Memory Application Based on IGZO Channel-All-Around Ferroelectric Field-Effect Transistors. Japanese Journal of Applied Physics, 63, 06SP05. [Google Scholar] [CrossRef] 
[15] Xu, L., Chen, K., Li, Z., Guo, J., Wang, L., Zhao, Y., et al. (2023) Reliability-Aware Ultra-Scaled IDG-InGaZnO-FET Compact Model to Enable Cross-Layer Co-Design for Highly Efficient Analog Computing in 2T0C-DRAM. 2023 International Electron Devices Meeting (IEDM), San Francisco, 9-13 December 2023, 1-4. [Google Scholar] [CrossRef] 
[16] Shi, M., Su, Y., Tang, J., Li, Y., Du, Y., An, R., et al. (2023) Counteractive Coupling IGZO/CNT Hybrid 2T0C DRAM Accelerating RRAM-Based Computing-in-Memory via Monolithic 3D Integration for Edge AI. 2023 International Electron Devices Meeting (IEDM), San Francisco, 9-13 December 2023, 1-4. [Google Scholar] [CrossRef] 
[17] Belmonte, A., Kundu, S., Subhechha, S., Chasin, A., Rassoul, N., Dekkers, H., et al. (2023) Lowest Ioff < 3×10−21 A/μm in Capacitorless DRAM Achieved by Reactive Ion Etch of IGZO-TFT. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, 11-16 June 2023, 1-2. [Google Scholar] [CrossRef] 
[18] Jeong, S. and Hong, S. (2024) Predicting the Retention Property of Scaled Cylindrical IGZO 2T0C DRAM Cells. 2024 IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, 15-16 June 2024, 123-124. [Google Scholar] [CrossRef] 
[19] Chen, H., Wu, C., Mudge, T. and Chakrabarti, C. (2016) RATT-ECC. ACM Transactions on Architecture and Code Optimization, 13, 1-24. [Google Scholar] [CrossRef] 
[20] Yan, S., Cong, Z., Lu, N., Yue, J. and Luo, Q. (2023) Recent Progress in InGaZnO FETs for High-Density 2T0C DRAM Applications. Science China Information Sciences, 66, Article No. 200404. [Google Scholar] [CrossRef] 
[21] Shi, M., Su, Y., Tang, J., Li, Y., Du, Y., An, R., et al. (2023) Counteractive Coupling IGZO/CNT Hybrid 2T0C DRAM Accelerating RRAM-Based Computing-in-Memory via Monolithic 3D Integration for Edge AI. 2023 International Electron Devices Meeting (IEDM), San Francisco, 9-13 December 2023, 1-4. [Google Scholar] [CrossRef]