基于FPGA的超混沌Chen同步视频加密系统设计与实现

Design and Implementation of Hyperchaotic Chen Synchronization Video Encryption System Based on FPGA

摘要: 针对实时高清视频加密中运算复杂度高与硬件资源消耗大的矛盾，本文设计并实现了一种基于FPGA的轻量化超混沌Chen同步视频加密系统。系统采用四维超混沌Chen系统作为密钥源，为降低高维算法的硬件开销，提出了一种基于时分复用状态机的轻量化混沌引擎，将8个乘法项压缩至单个硬件乘法器中实现。同时，针对底层硬件RGB565视频流特性，设计了位级异或流加密方案。通过MATLAB与ModelSim的联合仿真及Cyclone IV平台的实物验证表明：本系统在仅消耗23%逻辑资源和48%乘法器资源的前提下，实现了60 fps的零延迟视频加解密；密文相邻像素相关性低至0.0012，各通道直方图呈现理想的均匀分布。本研究为资源受限环境下的实时视觉安全提供了高效的硬件解决方案。

Abstract: To address the trade-off between high computational complexity and significant hardware resource consumption in real-time high-definition video encryption, this paper designs and implements a lightweight hyperchaotic Chen synchronization video encryption system based on FPGA. The system utilizes a four-dimensional hyperchaotic Chen system as the key source. To reduce the hardware overhead of high-dimensional algorithms, a lightweight chaotic engine based on a time-division multiplexing state machine is proposed, which compresses eight multiplication terms into a single hardware multiplier. Meanwhile, tailored to the characteristics of the underlying hardware RGB565 video stream, a bit-level XOR stream encryption scheme is designed. Verification results from MATLAB and ModelSim co-simulation, alongside physical tests on the Cyclone IV platform, demonstrate that the system achieves 60fps zero-latency video encryption and decryption while consuming only 23% of logic resources and 48% of multiplier resources. The correlation between adjacent pixels in the ciphertext is as low as 0.0012, and the histograms of all color channels exhibit an ideal uniform distribution. This research provides an efficient hardware solution for real-time vision security in resource-constrained environments.