多核数据管理器仲裁机制的研究与设计

Research and Design of Arbitration Mechanism for Multi-Core Data Manager

摘要: 多核片上数据传输是指在片上系统中，通过共享存储器、片上网络等方式进行通讯，实现多个处理器协同处理任务的技术。为了达到多核片上传输技术在进行多个处理器核和多个外部设备之间数据传输时，同时兼顾数据包发送和接收、有效监控数据交换和灵活派发数据包的目标，本文提出了一种基于大规模数据的拆解/封包传输的多核数据仲裁机制，新机制采用优先级多级调整策略，实现数据包有序进出队列管理器，从而减少内部通信方面的负担，提升系统整体性能，同时完成了新机制的HDL建模和仿真，实验结果表明，所提出的设计能够保证多组数据的优先级次序，提高传输时的数据利用率，平衡响应速度，在多数据场景下，实现公平有效地传输。

Abstract: Multi-core on-chip data transmission refers to a technology that communicates through shared memory, on-chip network, etc., in a system-on-chip to realize collaborative processing tasks by multiple processors. In order to achieve the goal of multi-core on-chip transmission technology in data transmission between multi-ple processor cores and multiple external devices, while taking into account data packet sending and receiving, effectively monitoring data exchange and flexibly dispatching data packets, this pa-per proposes a method based on a multi-core data arbitration mechanism for large-scale data dis-assembly/packet transmission. The new mechanism adopts a priority multi-level adjustment strategy to realize the orderly entry and exit of data packets into the queue manager, thereby re-ducing the burden of internal communication and improving the overall performance of the system. The HDL modeling and simulation of the new mechanism are carried out. The experimental results show that the proposed design can ensure the priority order of multiple groups of data, improve the data utilization rate during transmission, balance the response speed, and achieve fair and efficient transmission in multi-data scenarios.