基于40 nm数字芯片的复杂时钟结构分析及优化

Analysis and Optimization of Complex Clock Structure Based on 40 nm Digital Chip

摘要: 在复杂时钟结构芯片设计的物理实现中，基于Innovus工具采用传统时钟树综合流程得到的时钟树，具有时序违例大、插入缓冲器单元多、功耗大等问题，会给整个芯片设计带来挑战和困难。本文在传统时钟树流程基础上，采取在时钟树综合之前编写一个时序约束文件来分段长时钟树的方法进行改进优化。与传统方法的结果相比，最终得到一个级数较低的高质量时钟树，该时钟树时序违例小，违例路径减少85条，插入的缓冲器数目减少了2676个。新方法能有效地降低了芯片的总功耗以及节省了大量的空间面积，解决了局部绕线阻塞问题，并提高了芯片的工作性能。

Abstract: In the physical implementation of complex clock structure chip design, the clock tree obtained based on the Innovus tool using the traditional clock tree synthesis process has problems such as large timing violations, many insertion buffer units, and large power consumption, which will bring challenges and difficulties to the entire chip design. Based on the traditional clock tree process, this paper adopts the method of writing a timing constraint file to segment the clock tree before the clock tree synthesis. Compared with the results of the traditional method, a high-quality clock tree with a low series is obtained, which has small timing violations, 85 fewer illegal paths, and 2676 buffers inserted. The new method can effectively reduce the total power consumption of the chip, save a lot of space area, solve the problem of local winding blockage, and improve the working performance of the chip.